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swh/web/tests/resources/contents/code/extensions/test.vhd
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/* | |||||
* RS-trigger with assynch. reset | |||||
*/ | |||||
library ieee; | |||||
use ieee.std_logic_1164.all; | |||||
entity RS_trigger is | |||||
generic (T: Time := 0ns); | |||||
port ( R, S : in std_logic; | |||||
Q, nQ : out std_logic; | |||||
reset, clock : in std_logic ); | |||||
end RS_trigger; | |||||
architecture behaviour of RS_trigger is | |||||
signal QT: std_logic; -- Q(t) | |||||
begin | |||||
process(clock, reset) is | |||||
subtype RS is std_logic_vector (1 downto 0); | |||||
begin | |||||
if reset = '0' then | |||||
QT <= '0'; | |||||
else | |||||
if rising_edge(C) then | |||||
if not (R'stable(T) and S'stable(T)) then | |||||
QT <= 'X'; | |||||
else | |||||
case RS'(R&S) is | |||||
when "01" => QT <= '1'; | |||||
when "10" => QT <= '0'; | |||||
when "11" => QT <= 'X'; | |||||
when others => null; | |||||
end case; | |||||
end if; | |||||
end if; | |||||
end if; | |||||
end process; | |||||
Q <= QT; | |||||
nQ <= not QT; | |||||
end architecture behaviour; | |||||
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